The electrical characteristics of field effect transistors having submicron gate lengths can be degraded by field induced hot carrier injection parasitics and potentially high leakage currents. To inhibit these parasitic effects, field effect transistors have been formed with lightly doped drain (LDD) region extensions. However, conventional lightly doped drain region extensions typically increase the parasitic gate-to-drain capacitance and contribute to an increase in gate induced leakage currents at the drain. In addition, bipolar junction transistors having reduced dimensions can suffer from premature electrical field-induced breakdown at the emitter-base P-N junction when this junction is heavily reverse biased. Accordingly, when conventional steps for forming field effect transistors and bipolar junction transistors are merged into BiCMOS fabrication methods, the above described problems are compounded.